The present invention relates generally to operating memory cells of non-volatile memory (NVM) arrays, such as programming and erasing, and particularly to methods for reducing pulse operations of such arrays.
Memory cells are used in the implementation of many types of electronic devices and integrated circuits, such as, but not limited to, erasable, programmable read only memories (EPROMs), electrically erasable, programmable read only memories (EEPROMs), and flash EEPROM memories. Memory cells are used to store the data and other information for these and other integrated circuits.
Non-volatile memory (NVM) cells generally comprise transistors with programmable threshold voltages. For example, a floating gate transistor or a split gate transistor has a threshold voltage (Vt) that is programmed or erased by charging or discharging a floating gate located between a control gate and a channel in the transistor. Data is written in such memory cells by charging or discharging the floating gates of the memory cells to achieve threshold voltages corresponding to the data.
The act of programming the cell involves charging the floating gate with electrons, which increases the threshold voltage Vt. The act of erasing the cell involves removing electrons from the floating gate, which decreases the threshold voltage Vt.
One type of non-volatile cell is a nitride, read only memory (NROM) cell, described in U.S. Pat. No. 6,011,725, the disclosure of which is incorporated herein by reference. Programming and erasing of NROM cells are also described in U.S. Pat. No. 6,011,725.
Unlike a floating gate cell, the NROM cell has two separated and separately chargeable areas. Each chargeable area defines one bit The separately chargeable areas are found within a nitride layer formed in an oxide-nitride-oxide (ONO) stack underneath the gate. When programming a bit, channel hot electrons are injected into the nitride layer. This is generally accomplished by the application of a positive gate voltage and positive drain voltage, the magnitude and duration of which are determined by different factors related to the amount of programming required.
One preferred procedure for programming bits in NROM cells with programming pulses is described in Applicant""s copending U.S. patent application Ser. No. 09/730,586, entitled xe2x80x9cProgramming And Erasing Methods For An NROM Arrayxe2x80x9d, the disclosure of which is incorporated herein by reference.
The application of pulses to operate (program or erase) the NROM array may pose a problem for mass storage or code flash applications. For example, in programming a mass storage array, a major requirement is a fast programming rate, in the range of at least 2 MB/sec. The channel hot electron injection (CHE) used for programming may require a relatively high programming current, e.g., approximately 100xcexcA per cell. In addition, each programming step may comprise switching and subsequent verification steps. These factors may limit the amount of cells that may be programmed in parallel, to about 64 cells, for example.
Other complications that may hinder achieving fast, parallel programming rates include, among others, temperature dependence, cell length dependence (e.g., die to die and within a die), neighboring cell state dependence, second bit state dependence, and others. For example, FIG. 1 illustrates an effect of cell length on programming NROM cells. FIG. 1 illustrates the change in threshold voltage as a function of drain voltage used to program the cell. In the illustrated example, a first graph, denoted by the reference numeral 77, shows the change in threshold voltage as a function of drain voltage for a cell with a length of 0.5 microns. A second graph, denoted by the reference numeral 78, shows the change in threshold voltage as a function of drain voltage (Vd) for a cell with a length of 0.55 microns. It is seen that the slightly longer cell requires a higher drain voltage to achieve the same change in threshold voltage as the shorter cell.
As another example, FIG. 2 illustrates an effect of temperature on programming NROM cells. FIG. 2 illustrates the change in threshold voltage as a function of drain voltage (Vd) used to program the cell. In the illustrated example, a first graph, denoted by the reference numeral 79, shows the change in threshold voltage as a function of drain voltage in an ambient of 20xc2x0 C. A second graph, denoted by the reference numeral 80, shows the change in threshold voltage as a function of drain voltage in an ambient of 85xc2x0 C. It is seen that the warmer ambient requires a higher drain voltage to achieve the same change in threshold voltage as the cooler ambient.
Determination of programming pulses is also complicated by the fact that the cell parameters and operating conditions are usually initially unknown. Utilizing large programming pulse steps may reduce the total amount of programming pulses required to program the array. However, this may be disadvantageous because it may result in a wide and varied distribution of threshold voltages in the programmed cells of the array, which may reduce product reliability.
Alternatively, accurate verification of the cell threshold voltage and comparison of the threshold voltage to a variety of references may reduce the amount of programming pulses and provide faster convergence to the desired programmed threshold voltage level. However, such a method may incur a substantial overhead in the form of multiple verify pulses (e.g., one per reference), which is an undesirable time penalty, or may require an intricate parallel reference design, which is an undesirable chip area penalty.
The present invention seeks to provide methods for operating (programming or erasing) bits of memory cells in memory arrays, and for reducing pulse operations of such arrays. The invention is described in detail hereinbelow with reference to memory cells of NVM arrays, and particularly to NROM cells, wherein programming and erasing generally involve changing the threshold voltage level of a bit. However, it should be emphasized that the invention is not limited to NVM arrays, nor to changing the threshold voltage levels of bits. Rather, the present invention is applicable for any non-volatile or volatile memory array whose operation is based on changing any kind of electrical, physical and/or mechanical properties of the cell array. The invention may be implemented in a variety of applications, such as but not limited to, mass storage or code flash applications, for example.
In accordance with a preferred embodiment of the present invention, a small amount of cells in the array may be sampled to determine their behavior characteristics upon the application of pulses to program or erase. After learning how the threshold voltage changes in accordance with the pulses, the rest of the array may be programmed (or erased) en masse with a significantly reduced number of pulses and verifies. In some cases, the rest of the array may be programmed (or erased) with just one pulse.
There is thus provided in accordance with a preferred embodiment of the invention a method for operating bits of memory cells in a memory array, the method including applying operating pulses to bits of a sample of memory cells, determining a response of at least one of an electrical, physical and mechanical property (e.g., threshold voltage) of the bits to the operating pulses, and applying at least one further operating pulse to the rest of the array, the at least one further operating pulse being a function of the response.
In accordance with a preferred embodiment of the invention the method determines an operating pulse that singly changes the at least one of an electrical, physical and mechanical property of the bits a predefined amount.
Further in accordance with a preferred embodiment of the invention the method determines a programming pulse that singly increases the at least one of an electrical, physical and mechanical property of the bits a predefined amount.
Still further in accordance with a preferred embodiment of the invention the method determines an erasing pulse that singly lowers the at least one of an electrical, physical and mechanical property of the bits a predefined amount.
Additionally in accordance with a preferred embodiment of the invention the method includes applying the operating pulse (which may be modified by a tolerance) that singly changes the at least one of an electrical, physical and mechanical property of the bits the predefined amount.
In accordance with a preferred embodiment of the invention the method includes, after applying the at least one further operating pulse to the rest of the array, verifying the at least one of an electrical, physical and mechanical property of bits of the array to determine if the at least one of an electrical, physical and mechanical property has reached a predefined level. If the at least one of an electrical, physical and mechanical property of at least a portion of the bits has not yet reached the predefined level, then at least one more operating pulse may be applied to the at least a portion of the bits.